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semiconductor group 3 contents page 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 general functions and device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 individual functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5 additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 operating description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2 clocking, reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 control of layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6 information on literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7 semiconductor group - addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 iom ? , iom ? -1, iom ? -2, isac ? -p, isac ? -s, epic ? are registered trademarks of siemens ag general information

semiconductor group 5 06.92 preliminary data s/t bus interface circuit (sbc) cmos ic 1 features l full duplex 2b + d s/t-interface transceiver according to ccitt i.430 l conversion of the frame structure between the s/t and iom ? interfaces l d-channel access control l activation and deactivation procedures according to ccitt i.430 l built-in wake-up unit for activation from power-down state l adaptively switched receive thresholds l control via iom interface l several operating modes l receive timing recovery according to selected operating mode l frame alignment with absorption of phase wander in trunk line applications l switching of test loops l advanced cmos technology l low power consumption: peb 2080: standby less than 5 mw active max. 65 mw pef 2080: standby less than 6.5 mw active max. 70 mw type ordering code package peb 2080-n q67100-h8395 p-lcc-28-r (smd) peb 2080-p q67100-h2954 p-dip-22 pef 2080-n q67100-h6097 p-lcc-28-r (smd) peb 2080 pef 2080 p-lcc-28-r p-dip-22
semiconductor group 6 features the s-bus interface circuit (sbc) pex 2080 implements the four-wire s/t-interface used to link voice/data terminals to an isdn. through selection of operating mode, the device may be employed in all types of applications involving an s interface. two or more sbcs can be used to build a point- to-point, passive bus, extended passive bus or star configuration. specific isdn applications of the sbc include: isdn terminals, isdn network termination (central office and pabx applications), and pabx trunk lines to central office. the device provides all electrical and logical functions according to ccitt recommendation i.430. these include: mode-dependent receive timing recovery, d-channel access and priority control, and automatic handling of activation/deactivation procedures. the sbc does not require direct microprocessor control. the sbc is an iom compatible, 22-pin cmos device. it operates from a single + 5 v supply and features a power-down state with very low power consumption.
semiconductor group 7 pin configuration (top view) p-dip-22 p-lcc-28-r features
semiconductor group 8 features 1.1 pin definitions and functions pin no. p-lcc pin no. p-dip symbol input (i) output (o) function 3 2 sx1 o positive output s-bus transmitter 4 3 sx2 o negative output s-bus transmitter 7 5 sdo o serial data out, iom interface 10 8 sdi i serial data in, iom interface 8 6 dcl i/o serial data clock, iom interface 9 7 fsc i/o frame sync, iom interface 16 5 20 12 4 15 m2 m1 m0 i i i setting of operation mode 14 11 19 17 11 9 14 13 x3 x2 x1 x0 i i/o i/o i/o functions depending on the selected operating mode see chapter 2.2 21 16 cp i/o clock pulse/special purpose 24 19 xtal1 i connection for external crystal, or input for external clock generator 23 18 xtal2 o connection for external crystal, n.c. when external clock generator is used 26 20 sr2 i s-bus receiver, signal input 27 21 sr1 o s-bus receiver, 2.5 v reference output 2 1 vdd i power supply, + 5 v 5 % 22 17 vss i power supply, ground 13 10 rst i reset, active low 6 - x4 i external filter connection, active low 28 - ufi o opamp output for external filter 25 - aux i auxiliary input: v dd or v ss to be applied 15 18 1 - - - n.c. - - - not connected
semiconductor group 9 features logic symbol
semiconductor group 10 features block diagram
semiconductor group 11 features 1.2 system integration the sbc implements the four-wire s and t interfaces used in the isdn basic access. it may be used at both ends of these interfaces. the applications include: isdn terminals (te) isdn network termination (nt) isdn subscriber line termination (lt-s) isdn trunk line termination (lt-t) (pabx connection to central office). these applications are shown in figure 1 , where the usual nomenclature as defined by the ccitt for the basic access functional blocks and reference points, has been used. figure 1 applications of sbc
semiconductor group 12 features some of the s interface wiring configurations possible with the sbc are shown in figure 2 with approximate typical distances. *) (n.b.: tr stands for terminating resistor of value 100 w ). figure 2 some s-interface wiring configurations *) the maximum line attenuation tolerated by the sbc is 10 db at 96 khz
semiconductor group 13 figure 3 isdn oriented modular (iom ? ) architecture
semiconductor group 14 figure 3 gives an example of an application of the sbc in an iom (isdn oriented modular) architecture. by separate implementation of osi layer-1 and layer-2 functions, and through unified control procedures, the architecture provides flexibility with respect to various transmission techniques. the iom devices are all low-power, high integration, single + 5 v supply cmos devices. through mode switching, each device may be used in several applications: thus with one and the same limited set of devices all isdn basic access configurations are covered. note that one of the compatible layer-1 devices (sbc, ibc, iec) requires direct microprocessor control. this is, of course, due to the fact that the iom interface provides all the necessary functions for layer-1/layer- 2 communication.
semiconductor group 15
semiconductor group 15 2 functional description the s-bus interface circuit pex 2080 performs the layer-1 functions for the s/t interface of the isdn basic access. 2.1 general functions and device architecture the common functions for all operating modes are: l iine transceiver functions for the s interface according to the electrical specifications of ccitt i.430; l dynamically adaptive threshold control for the receiver; l conversion of the frame structure between iom and s interfaces; l conversion from/to binary to/from pseudo-ternary code. mode specific functions are: l receive timing recovery; l s-timing generation using iom timing synchronous to system, or vice versa; l d-channel access control and priority handling; l d-channel echo bit generation; l activation/deactivation procedures, triggered by primitives received over the iom interface or by infos received from the line; l frame alignment according to ccitt q.503; l execution of test loops. analog functions the full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a current limited voltage source. a voltage of 2.1 v is delivered between sx1-sx2, which yields a current of 7.5 ma over 280 w . the receiver is designed as a threshold detector with adaptively switched threshold levels. pin sr1 delivers 2.5 v as an output, which is the virtual ground of the input signal on pin sr2. an external transformer of ratio 2:1 is needed in both receive and transmit direction to provide for isolation and transform voltage levels according to ccitt recommendations. functional description
semiconductor group 16 functional description digital functions a dpll circuitry working with a frequency of 7.68 mhz 100 ppm serves to generate the 192-khz line clock from the reference clock delivered by the network and to extract the 192-khz line clock from the receive data stream. the 7.68-mhz clock may be generated with the use of an external crystal between pins xtal1 and xtal2. it may also be provided by an external oscillator, in which case xtal2 is left unconnected. the control block includes the logic to detect layer-1 commands and to communicate with external layer-1 or layer-2 devices via the iom interface. an incorporated finite state machine controls isdn layer-1 activation/deactivation. the d-channel access procedure according to ccitt i.430 including priority management is fully implemented in the sbc. when used as an s-bus master in a multipoint configuration, the device generates the echo bits necessary for d-channel collision detection. in the nt-mode, moreover, the echo channel may be made externally available through an auxiliary pin and thus intelligent nts (star configuration) may be implemented. in terminal applications (te) the q channel as specified by i.430 is supported (stepping a6 and up. the sbc sends a binary one in f a -bit position to allow another terminal to use the extra transmission capacity.) the buffer memory serves to adapt the different bit rates of the s and the iom interface. in addition, in trunk line applications it absorbs the possible deviation between two system clocks, according to ccitt q.503 (slip detection). 2.2 operating modes the operating modes are determined by pin strapping on pins m0 to m2. the four basic operating modes are: te, nt, lt-s, lt-t. in three of these operating modes, the iom may be programmed to function in the iom-1 mode, in the iom -2 mode or in the inverted mode. to see which iom timing mode is applicable in the four basic operating modes, refer to table 1 . in table 1 , the functions of the operating mode specific pins are given: these pins are dcl (iom interface data clock, input/output), fsc (iom interface frame sync, input/output), cp (auxiliary clock/test pin), and x0 to x3. depending on the selected mode, pins cp, x2 and x1 provide auxiliary clocks, either asynchronous or synchronous to the s-interface: these auxiliary clocks may be used to drive, e.g. a codec filter, or a microprocessor system (te applications). 3840 khz 2560 khz 1280 khz clocks derived from the 7680-khz crystal 1536 khz 512 khz clocks synchronized to s interface
semiconductor group 17 functional description table 1 operating modes and functions of mode specific pins of sbc *) synchronized to s/t interface i:input o:output application te te te lt-t lt-t nt lt-s lt-s lt-s operation of iom interface inverted mode inverted mode iom-1 mode iom-2 mode or invert. mode iom-1 mode iom-1 mode iom-2 mode or invert. mode iom-1 mode iom-1 mode m2 m1 m0 0 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 0 dcl o: 512 khz* o: 512 khz* o: 512 khz* i: 4096 khz i: 512 khz i: 512 khz i: 4096 khz i: 512 khz i: 512 khz fsc o: 8 khz* o: 8 khz* o: 8 khz* i: 8 khz i: 8 khz i: 8 khz i: 8 khz i: 8 khz i: 8 khz cp o: 1536 khz* o: 1536 khz* o: 512 khz* o: 512 khz* o: 512 khz* i: scz i:fixed at 0 i:fixed at 0 i:fixed at 0 x3 i: enck i: enck i: enck i:fixed at 1 i:fixed at 0 i:bus i:bus i:bus i:bus x2 o: 2560 khz o: 1280 khz o: echo i:ts2 i:fixed at 0 i: ssz i:ts2 i:fixed at 0 o: 192 khz* x1 o: 3840 khz o: 3840 khz o: 3840 khz i:ts1 i:fixed at 0 i:dex i:ts1 o: 7680 khz o: 7680 khz x0 o:rdy o:rdy i:con i:ts0 i:con i/o:de i:ts0 i:fixed at 0 i:fixed at 1
semiconductor group 18 functional description the other uses of the auxiliary pins are: enck input enable clock. at 0, forces the sbc to deliver iom timing at all times, regardless of sdi input level; in te mode, pin x3. bus input at 1, specifies a bus configuration (as opposed to point to point or extended passive bus); in nt and lt-s modes, pin x3. echo output push-pull reproduces the e bits received from the s interface synchronously to iom frame d bits (bit positions 24 and 25 of iom frame). all other bit positions are binary 1; in te mode, pin x2. ssz input send single zeros. at 0, forces the sbc to transmit alternating pulses at 250 s intervals (period 2 khz) on s-interface for test purposes; x2 in nt mode. rdy output ready. provides a signal logically equal push to bit 3 of monitor channel. signals the pull d-channel status (0 = occupied, 1 = free) to layer-2 component; x0 in te mode. con input connected. at 0, prevents the sbc from activating and transmitting on the s interface. indicates whether the device is connected to the s interface or not; x0 in te and lt-t modes. dex input external d-channel echo enable. at 1, makes the e-bit dependent on the de (x0) input. used in nt mode to build a star configuration; x1 in nt mode. de input/output open drain with integrated pull- up resistor d-channel echo. the de outputs should be tied together (open drain) in an nt-star configuration, to obtain the global echo bit; x0 in nt mode. ts0 to ts2 inputs time slot 0 to 7. iom interface time slot to be used = 4 x ts2 + 2 x ts1 + ts0; lt-t and lt-s in iom-2 mode and inverted mode.
semiconductor group 19 functional description figure 4 clocking of sbc in different operating modes
semiconductor group 20 functional description 2.3 interfaces s interface according to ccitt recommendation i.430, pseudo-ternary encoding with 100 % pulse width is used on the s interface. a logical 1 corresponds to a neutral level (no current), whereas logical 0s are encoded as alternating positive and negative pulses. an example is shown in figure 5 . figure 5 s-interface line code one s frame consists of 48 bits, at a nominal bit rate of 192 kbit/s. thus each frame carries two octets of b1, two octets of b2, and four d bits, according to the b1 + b2 + d structure defined for the isdn basic access (total useful data rate: 144 kbit/s). frame begin is marked using a code violation (no mark inversion). the frame structures (from network to subscriber, and subscriber to network) are shown in figure 6 . figure 6 frame structure at reference ponts s and t (ccitt i.430)
semiconductor group 21 functional description digital interface iom frame structure the sbc is provided with a digital interface, the iom interface, for communication with other isdn devices, in other words with units realizing osi layer-1 functions (such as the isdn echo cancellation circuit iec peb 2090) or layer-2 functions (such as the isdn communication controller icc peb 2070). the iom interface is a four-wire serial interface with: a bit clock, a frame clock and one data line per direction ( figure 7 ). the isdn data rate of 144 kbit/s (b1 + b2 + d) is transmitted transparently in both directions over the interface. in addition, it is necessary to interchange control information for activation and deactivation of osi layer 1 and for switching of test loops. this information is transferred using time division multiplexing with a 125- m s total frame length. figure 7 iom ? interface signals
semiconductor group 22 functional description the basic frame consists of a total of 32 bits, or four octets: b1 + b2 + d (18 bits) plus 14 bits of monitor and control information. the data in both directions are synchronous and in phase ( figure 8 ). figure 8 iom ? interface frame structure 1st octet b1: b channel (64 kbit/s), most significant bit first 2nd octet b2 -- -- 3rd octet: monitor channel (64 kbit/s) -- 4th octet b*: 2-bit d channel (16 kbit/s) 4-bit c/i channel t channel: not used with sbc e bit: not used with sbc. the c/l channel is used for communication between the sbc and a processor via a layer-2 device, to control and monitor layer-1 functions. the codes originating from layer-2 devices are called commands, those sent by the sbc are called indications. for a list of the c/l codes and their use, refer to chapter 4. three modes of the lom are distinguished. these modes differ only with respect to the physical data rate (256 or 8 x 256 kbit/s) and to polarity of the clocks.
semiconductor group 23 functional description iom-1 mode this timing mode is applicable in all operating modes of the sbc. nominal bit rate of data (sdi and sdo): 256 kbit/s nominal frequency of dcl: 512 khz nominal frequency of fsc: 8 khz transitions of the data occur after even-numbered rising edges of dcl. even-numbered rising edges of the clock are defined as the second rising edge following the rising edge of fsc and every second rising edge thereafter. the frame is earmarked by the rising edge of fsc. figure 9 timing of data and clocks of iom ? in the normal mode inverted mode timing mode applicable in te mode: 512 khz the characteristics are the same as above, except that fsc is not a signal with 50 %, duty cyc!e but an active low pulse, one dcl clock period long, which occurs in the middle of bit 27 (fourth bit of b*). timing mode applicable in lt-t and lt-s operating modes: 4096 khz nominal bit rate of data bursts (sdi and sdo) 2048 kbit/s nominal frequency of dcl 4096 khz nominal frequency of fsc 8 khz. the frame clock fsc is an active low strobe clock. the strobe earmarks the second half of bit no. 251 in the frame. the low state of the strobe is detected with the rising edge of dcl. refer to figure 10 . the data at the input sdi is valid on the even-numbered rising edges of dcl. transitions of the data on sdo occur after even-numbered falling edges of dcl. the rising edge earmarked by the frame strobe is an even-numbered rising edge of dcl. the following falling edge is an even-numbered falling edge.
semiconductor group 24 functional description the bursts are allocated to consecutive time slots in a frame by the static inputs x0 (ts0), x1 (ts1), x2 (ts2). table 2 indicates the allocations. figure 11 gives the positions of the respective frames. figure 10 timing of data and clocks of iom ? in the inverted mux mode iom ? -2 mode timing mode applicable in lt-t and lt-s modes: 4096 khz. as opposed to inverted mode, data change with rising edges and frame synchronization is defined as in iom-1 mode. (cf. iom ? interface specification, rev. 2.2). table 2 allocation of time slots time slot no. ts2 ts1 ts0 bit no. 0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111 0 31 32 63 64 95 96 127 128 159 160 191 192 223 224 255
semiconductor group 25 functional description figure 11 position of iom ? frames as a function of time slot allocation in iom ? -2 and inverted mode
semiconductor group 26 functional description the iom-2 mode may be used to link up to eight sbcs over a single 2048 kbit/s interface to an exchange or pabx ( figure 12 ). figure 12 iom ? interface 2048 kbit/s mux mode
semiconductor group 27 functional description 2.4 individual functions the sbc transmits data between the iom interface and the line interface. the relative frame positions have been selected to minimize the round trip delays of the b channels, which are: 125 m s for te, nt and lt-s in normal iom mode, max. 250 m s for lt-t in normal iom mode and lt-s in inverted mux mode and, finally, max. 375 m s for lt-t in inverted mux mode. in the active state the data of the b channels are switched through transparently. the same applies to the d channel, except in te mode where d-channel switching is subject to the s bus d-channel access procedure and collision detection. s/t interface pre-filter in some applications it may be desirable to improve the signal-to-noise ratio of the received s/t interface signal by filtering out undesirable frequency (usually high frequency) components. this may be realized by an external pre-filter. to simplify the implementation of this filter, an operational amplifier is integrated in the isac-s, as shown in figure 13 . by connecting an rc network between input sr2 and the extra pin ufi an active rc filter of desired order can be realized (one example is shown in figure 13b ). figure 13a prefilter connections
semiconductor group 28 functional description figure 13b example of 2 nd order rc network note: following component values are recommended to give a 500 khz cutoff, and 600 ns ( 170 ns) propagation delay time: r 1 = r 2 =10k w c 1 =13pf c 2 = 22.5 pf an extra delay may be introduced into the received signal by a filter.
semiconductor group 29 functional description nt and lt-s applications the 192-khz transmit bit clock is synchronized to the iom clock dcl. in the receive direction two cases have to be distinguished depending whether a bus or a point-to-point operation is programmed (pin x3:bus). bus operation the 192-khz receive bit clock is identical to the transmit bit clock, shifted by 4.6 m s with respect to the transmit edge. according to ccitt i.430, the receive frame shall be shifted by two bits with respect to the transmit frame. point-to-point operation the 192-khz receive bit clock is recovered from the receive data stream on the s interface (the sampling instant for the receive bits is shifted by 3.9 m s with respect to the leading edge of the derived receive clock). according to ccitt i.430, the receive frame can be shifted by 2-8 bits with respect to the transmit frame at the nt (lt-s) (other shifts are allowed by sbc (including 0)). this operation mode should also be used in extended passive bus applications. e channel handling for d-channel access collision resolution, the received d bit is in all cases transmitted as the e bit in the s-frames. in addition, in the nt mode the echo bit may be made externally available, thus allowing for the implementation of a star configuration. te application the transmit and receive bit clocks are derived, with the help of the dpll, from the s-interface receive data strem. the transmit frame is shifted by two bits with respect to the received frame. the output clocks cp, dcl and fsc are synchronous to the s-interface timing.
semiconductor group 30 functional description figure 14 clock system of the sbc
semiconductor group 31 functional description d-channel access control the d-channel access control ensures that only one terminal shall have access to the d channel at any time. this is achieved through collision detection by each terminal (ccitt i.430). the sbc monitors the received d-echo channel, and, when transmission in the d channel is started, compares the echo bits to the transmitted d bits. a mismatch between d bit and d-echo bit means that another terminal is also transmitting and a collision has taken place. this can only happen if d = 1 and d-echo = 0, since on the s bus a logical 0 overrides a logical 1 (thus the comparison of d echo with d bit is performed only when d echo = logical 0). the sbc immediately ceases transmission, returns to the d-channel monitoring state and sends 1s in the d channel. d-channel access is possible only after x consecutive 1s have been received in the echo channel. depending on the priority class, x can be either eight or ten. if a terminal has successfully transmitted a complete hdlc frame, x is automatically increased by 1. x is reset to its initial value of eight (ten) when nine (eleven) consecutive 1s are received in the echo channel. to enable initiating and interrupting hdlc frame transmission in the d channel, the sbc has to inform the layer-2 controller (isdn communication controller) of the d-channel status ready or busy. for this, bit 20 of the iom frame, in other words the fourth bit from the right in the monitor channel, is used: see figure 15 . figure 15 position of busy bit in iom ? frame d c/i t e d s-bus d-channel busy = 1 not available s-bus d-channel busy = 0 available sdo b1 b2 monitor b*
semiconductor group 32 functional description by sending the busy bit at 0 to the isdn communication controller in anticipation of the s-bus d- channel ready state, the first valid d bits will emerge from the sbc at exactly the moment an access is allowed. d-channel switching (blocked: d = 1, or transparent: d = hdlc) is described by the state diagram in figure 15a with busy bit states ready and busy as input variables. figure 15b shows the status diagram for ready and busy, with the following variables: p: priority (8 or 10), set by a c/l channel command c: number of consecutive ones appearing in the echo channel v: v = 1 if: transmitted d bit = received d-echo bit v = 0 otherwise d p : priority decrement for priority class p (p = 8 or 10). thus state 1 is the state where a d-channel access may be attempted. the transition 1 - 2 occurs at the first zero of an opening flag (c = 0: zero observed in d-echo channel, and v = 1: a zero has actually been transmitted). transition i - 0 (i = 1,2,3) occurs at the first monitored zero in the echo channel when the station is idle (1 - 0), or if a collision either within an opening flag (2 - 0) or between the opening and closing flags (3 - 0) of an hdlc frame is observed. the successful transmission of a closing flag (3 - 0 conditioned by c = 6) must be followed by a decrement in the priority class (d p = 1 ). d p is reset when 9 or 11 consecutive 1s are observed (state 1): cf ccitt i.430.
semiconductor group 33 functional description figure 16 d-channel access control of the sbc
semiconductor group 34 functional description q channel the sbc provides q-channel support by transmitting a binary 1 in each frame in which a 1 is received in the f a -bit position of the nt-to-te frame. thus interference of f a bits from one te with the q bits in passive bus configurations is avoided. lt-t application as in te applications, the receive 192-khz clock is adaptively derived from the s-interface data. the transmit frame is shifted by two bits with respect to the receive frame. the sbc provides a 512-khz clock, cp, derived from the 192-khz receive line clock with the dpll. if necessary, this reference clock may be used to synchronize the central system (nt2) clock generator. the system timing is input over iom interface bit and frame clocks, dcl and fsc. the relative position of the s and iom frame is arbitrary. moreover, the sbc prevents a slip from occurring if the wander between the dcl and cp clocks does not exceed a limit (the sbc enables intermediate storage of: 3xb 1 , 3xb 2 and four d bits, for phase difference and wander absorption). ln case a wander greater than 24 m s is exceeded (cf ccitt q.503), a warning is sent twice by the sbc in the c/l channel (slip). if the analog test loop (tl3) is closed, the 192-khz line clock is internally derived from dcl: therefore no slips can occur in this case. since only point to point configurations can be realized with the lt-t application, bus availability indication is not required. however, the d-echo bit is still monitored and interference-free transmission is indicated by the busy bit.
semiconductor group 35 functional description 2.5 additional functions test functions test loops two kinds of test loops may be closed in the sbc, which depend on the selected mode of operation. in both test loops, all three channels (b1, b2 and d) are looped back. in a transparent loop the data are also sent forward (in addition to being looped back), whereas in a non-transparent loop the forward data path is blocked (ccitt i.430). these test loops are shown in figure 17 . figure 17 test loops of sbc test loop 3 is activated with the c/l channel command activate request loop (arl). an s interface is not required since info3 is looped back to the receiver. when the receiver has synchronized itself to this signal, the message test indication (or awake test indication) is delivered in the c/l channel. no signal is transmitted over the s interface. test loop 2 is likewise activated over the iom interface with activate request loop (arl). no s line is required. info4 is looped back to the receiver and also sent to the s interface. when the receiver is synchronized, the message aiu is sent in the c/l channel. in the test loop mode the s-interface awake detector is disabled, and echo bits are set to logical 0.
semiconductor group 36 functional description test signals two kinds of test signals may be sent by the sbc: single pulses and continuous pulses. the single pulses are of alternating polarity, one s-interface bit period wide, 0.25 ms apart, with a repetition frequency 2 khz. single pulses can be sent in all applications. the corresponding c/l command in te, lt-s and lt-t applications is ssz (send single zeros). alternatively, this test mode can be effected by pulling pin ssz (pin x2, nt mode only) to logical 0. continuous pulses are likewise of alternating polarity, one s-interface bit period wide, but they are sent continuously. the repetition frequency is 96 khz. continuous pulses may be transmitted in all applications. this test mode is entered in lt- s, lt-t and te applications with the c/l command scz. alternatively, pin scz (pin cp, nt mode only) can be pulled to logical 0. special applications the mode specific pins x0-3 allow for special applications to be implemented, some of which are mentioned in the following. star configuration in nt mode, the sbc transmits the d-bit state over pin x0 (de). a star configuration may be implemented by connecting pins x0 of several sbcs together (open drain with integrated pull up). with x1 (dex, d -e- ex ternal mirrowing) tied to logical 1, the sbc transmits the resulting de (wired and for all sbcs) as the s-interface echo bit. see figure 18 . figure 18 star configuration in nt
semiconductor group 37 functional description use of echo local communication of terminals connected to an s bus may be implemented by using the auxiliary echo output (pin x2, in te mode only). the timing of echo is identical to that of output sdo: however, the signal is 1 everywhere except in bit positions 24 and 25 of the iom frame, where it is equal to the echo bits received from the s interface. thus a layer-2 device (e.g. the isdn communication controller peb 2070) connected to echo is able to receive or hear all other terminals. as a special application, an s-bus local area network may be built using several te sbcs and one nt (or an nt star configuration). communication in the d and e channel is half duplex. figure 19 star configuration in nt
semiconductor group 38 3 operational description 3.1 general the internal finite state machine of the sbc controls the activation/deactivation procedures, switching of test loops and transmission of special pulse patterns. such actions can be initiated by signals on the s transmission line (infos) or by control (c/l) codes sent over the iom interface. the exchange of control information in the c/l channel is state oriented. this means that a code in the c/l channel is repeated in every iom frame until a change is necessary. a new code must be found in two consecutive iom frames to be considered valid (double last look criterion). 3.2 clocking, reset and initialization in lt-t and lt-s applications the iom interface should be kept active, i.e. the clocks dcl and fsc are always present. in this case commands in the c/l channel may also be handed over to the sbc in the power down state (state f3 for lt-t/state g1 for lt-s: see figures 24 and 25 ). in te and nt applications the iom interface can be switched off in the inactive state, reducing power consumption to a minimum (on the order of 5 mw and 6.5 mw for peb and pef, respectively). in this deactivated state the clock lines are low and the data lines are high. for the te case the procedure is shown in figure 20 . after detecting the code diu (deactivate indication upstream, i.e. from te to nt/lt-s) from the downstream unit, the sbc responds by transmitting did (deactivate indication downstream) during subsequent frames and stops the timing signals synchronously with the end of the last c/l channel bit of the fourth frame. figure 20 deactivation of the iom ? interface operational description
semiconductor group 39 operational description in nt mode the iom interface is activated by the upstream unit turning on the clocking signals. simultaneously the upstream unit must send the desired command in the c/l channel. in the case where activation is requested from a terminal, the nt sbc first requests timing on the iom interface by pulling sdo to a static low level. the sbc enters the power-up state immediately after timing has been applied. the clock signals may be switched off after the code deactivation indication downstream has been sent twice by the upstream unit. figure 21 activation of the iom ? interface
semiconductor group 40 operational description as an alternative to clock activation via sdi, the asynchronous wake-up pin enck (x3 in te mode) can be grounded. in this case the timing given in figure 22 applies. when enck is tied to ground the iom-clock pulses are delivered by sbc at all times. figure 22 activation of the iom ? interface via enck (pin x3) in te mode (nb: dcl out of scale) the clock pulses will be enabled again when the sbc recognizes a low level on sdi (command timing tim = 0000) or when a non-zero level on the s line interface is detected. the clocks are turned on after approximately 0.5 to 4 ms (dependent on the capacitances on xtal 1/2). after the clocks have been enabled this is indicated by the pu code in the c/l channel. the downstream unit may then insert a valid code in the c/l channel. the continuous supply of timing signals by the sbc is ensured as long as there is no diu command in the c/l channel. if timing signals are no longer required and activation is not yet requested, the downstream unit may indicate this by sending diu. at power up, a reset pulse ( rst) should be applied to bring the sbc to a well defined state. this state is g1 for nt or lt-s mode, and f3 for te or lt-t mode. the oscillator and energy intensive analog components are disabled and the s-line awake detector is active after the pulse. all outputs are in high impedance state during the hardware reset pulse. in te mode when enck is grounded, however, the sbc will still supply iom timing during a reset pulse, and the message error indication ei is present in the c/l channel. similarly, in nt mode, activation of pin cp brings the outputs to low impedance during a reset pulse and the message ei is sent in the c/l channel.
semiconductor group 41 operational description 3.3 control of layer 1 the state diagrams are shown in figures 24 to 26 . the activation/deactivation implemented by the sbc in its different operating modes agrees with the requirements set forth in ccitt re- commendations. state identifiers f1-f8 (te/lt-t) and g1-g4 (nt/lt-s) are in keeping with ccitt i.430. in the nt mode the four states have been expanded to implement a full handshake between the ends of the subscriber loop. in the state diagrams a notation is employed which explicitly specifies the inputs and outputs on the s interface and in the c/l channel: see figure 23 . figure 23
semiconductor group 42 operational description commands / indications and state diagrams in te / lt-t table 5 (x) unconditional commands command (upstream) abbr. code remark timing tim 0000 activation of all output clocks is requested reset rs 0001 (x) send continuous zeros scz 0100 transmission of pseudo-ternary pulses at 96-khz frequency (x) send single zeros ssz 0010 transmission of pseudo-ternary pulses at 2-khz frequency (x) activate request, set priority 8 ar8 1000 activation command, set d-channel priority to 8 activate request, set priority 10 ar10 1001 activation command, set d-channel priority to 10 activate request loop arl 1010 activation of test loop 3 (x) deactivate indication diu 1111 iom interface can be disabled indication (downstream) abbr. code remark power up pu 0111 iom clocking is provided deactivate request dr 0000 deactivation request by s slip detected sd 0010 wander is larger than 24 m s peak-to-peak disconnected dis 0011 pin con connected to gnd error indication ei 0110 ( rst = 0 & enck = 0) in te, or rs level detected rsy 0100 signal received, receiver not synchronous activate request ard 1000 info 2 received test indication ti 1010 test loop 3 activated or continuous zeros transmitted awake test indication ati 1011 level detected during test loop activate indication with priority class 8 ai 8 1100 info 4 received, d-channel priority is 8 or 9 activate indication with priority class 10 ai 10 1101 info 4 received, d-channel priority is 10 or 11 deactivate indication did 1111 clocks will be disabled, (in te), quiescent state
semiconductor group 43 operational description te / lt-t mode f3 power down this is the deactivated state of the physical protocol.the receive line awake unit is active except during a rst pulse. clocks are disabled if enck = 1 (te mode). the power consumption in this state is approximately 22 mw when the clock is running, and 4 mw otherwise. f3 power up this state is identical to f3 power down, except for the c/l output message. the state is invoked by a c/l command tim = 0000 (or sdi static low). after the subsequent activation of the clocks the pu message is outputted. this occurs 0,5 ms to 4 ms after application of tim, depending on crystal capacitances. if, however, the sbc is disconnected from the s interface (con = 0), the c/l message dis is outputted. f3 pend. deact. the sbc reaches this state after receiving info0 (from states f5 to f8) for 16 ms (64 frames). this time constant is a flywheel to prevent accidental deactivation. from this state an activation is only possible from the line (transition f3 pend. deact. to f5 unsynchronized). a power down state may be reached only after receiving diu. f4 pend. act. activation has been requested from the terminal, info1 is transmitted, info0 is still received, power up is transmitted in the c/l channel. this state is stable: timer t3 (i.430) is to be implemented in software. f5 unsynchronized at the reception of any signal from the nt, the sbc ceases to transmit info1 and awaits identification of info2 or info4. this state is reached at most 50 s after a signal different from info0 is present at the receiver of the sbc. f6 synchronized when the sbc receives an activation signal (info2), it responds with info3 and waits for normal frames (info4). this state is reached at most 6 ms after an info2 arrives at the sbc (when the oscillator was disabled in f3 power down). f7 activated this is the normal active state with the layer-1 protocol activated in both directions. from state f6 synchronized, state f7 is reached at most 0,5 ms after reception of info4. from state f3 power down with the oscillator disabled, state f7 is reached at most 6 ms after the sbc is directly activated by info4. f8 lost framing this is the condition where sbc has lost frame synchronization and is awaiting re-synchronization by info2 or info4 or deactivation by info0.
semiconductor group 44 operational description unconditional states loop3 closed on activate request loop command, info3 is sent by the line transmitter internally to the line receiver (info0 is transmitted to the line). the receiver is not yet synchronized. loop3 activated the receiver is synchronized on info3 which is looped back internally from the transmitter. data may be sent. the indication tl orati is output depending whether or not a signal different from info0 is detected on the s interface. test mode continuous pulses continuous alternating pulses are sent. test mode single pulses single alternating pulses are sent (2-khz repetition rate). reset state a software reset (rs) forces the sbc to an idle state where the analog components are disabled (transmission of info0) and the s line awake detector is inactive. thus activation from the nt is not possible. clocks are still supplied (te mode) and the outputs are in a low impedance state.
semiconductor group 45 operational description figure 24a state diagram of te/lt-t mode
semiconductor group 46 operational description figure 24b state diagram of te/lt-t mode: unconditional transitions
semiconductor group 47 operational description commands / indications and state diagrams in lt-s mode table 3 (x) unconditional commands command (downstream) abbr. code remark deactivate request dr 0000 (x) send continuous zeros scz 0010 transmission of pseudo-ternary pulses at 96-khz frequency (x) send single zeros ssz 0010 transmission of pseudo-ternary pulses at 2-khz frequency (x) activate request ard 1000 activate request loop arl 1010 activation request for loop 2 deactivate indication did 1111 deactivation acknowledgement, quiescent state indication (upstream) abbr. code remark lost signal level lsl 0001 no receive signal lost framing rsyu 0100 receiver is not synchronous activate request aru 1000 info 1 received activate indication aiu 1100 synchronous receiver deactivate indication diu 1111 timer (32 ms) expired or info 0 received (during 16 ms) after deactivation request
semiconductor group 48 operational description lt-s mode g1 deactivated the sbc is not transmitting. no signal detected on the s interface, and no activation command is received in c/l channel. g2 synchronized as a result of an info1 detected on the s line or an ard command, the sbc begins transmitting info2 and waits for reception of info3. info2 is sent after the awake detector has detected pulses during 4 ms. the timer to supervise reception of info3 is to be implemented in software. g3 activated normal state where info4 is transmitted to the s interface. this state is reached less than 2 ms after an info3 first arrives at the sbc receiver. the sbc remains in this state as long as neither a deactivation or a test mode is requested, nor a reset pulse is issued. when receiver synchronism is lost, lnfo2 is sent automatically. after reception of info3, the transmitter keeps on sending info4. (version a7 and following) g4 pend. deact. this state is triggered by a deactivation request dr. it is an unstable state: indication diu (state g4 unackn.) is issued by the sbc when: C either info0 is received during 16 ms, C or an internal timer of 32 ms expires. g4 unacknowleded final state after a deactivation request. the sbc remains in this state until a response to diu (in other words did) is issued, without which a new activation is impossible. test mode continuous pulses continuous alternating pulses are sent. test mode single pulses single alternating pulses are sent (2-khz repetition rate).
semiconductor group 49 operational description figure 25 state diagram of lt-s mode
semiconductor group 50 operational description commands / indications and state diagrams in nt table 4 (x) unconditional commands command (downstream) abbr. code remark deactivate request dr 0000 (x) resynchronization of u-interface rsyd 0100 transmission of pseudo-ternary pulses at 96-khz frequency after loss of synchronism of the u interface activate request ard 1000 transmission of info 2 activate request loop arl 1010 transmission of info 2, switching of test loop 2 deactivate indication did 1111 deactivation acknowledgement, quiscent state activate indication aid 1100 transmission of info 4 activate indication loop ail 1110 transmission of info 4, switching of test loop 2 send single zeros ssz 0010 transmission of pseudo-ternary pulses at 2-khz frequency (x) indication (upstream) abbr. code remark timing tim 0000 sbc requires clock pulses lost signal level lsl 0001 no receive level lost framing rsyu 0100 receiver is not synchronous error indication ei 0110 rst and scz both active activate request aru 1000 info 1 received activate indication aiu 1100 synchronous receiver deactivate indication diu 1111 timer (32 ms) expired or info 0 received (during 16 ms) after deactivation request
semiconductor group 51 operational description nt mode g1 deactivated the sbc is not transmitting. no signal is detected on the s/t interface, and no activation command is received in c/l channel. ei is output as a response to rst, diu is output in the normal deactivated state, and tim is output as a first step when an activation is requested from the s/t interface. g1 i1 detected an info1 is detected on the s/t interface, translated to an activation request upstream indication in the c/l channel. the sbc is waiting for an ard command, which normally indicates that the transmission line upstream (usually a two-wire interface) is synchronized. g2 pend. act. as a result of the ard command, an info2 is sent on the s/t interface. info3 is not yet received. g2 synchronized info3 was received, info2 continues to be transmitted while the sbc waits for a switch-through command aid from the device upstream. g3 activated info4 is sent on the s/t interface as a result of the switch through command aid: the b and d channels are transparent. in case of loss of synchronism of the nt receiver, lnfo2 is sent (version a7 and following). lost framing u on receiving a rsyd command which usually indicates that synchronization has been lost on the two-wire interface, the sbc transmits continuous alternating pulses. g4 pend. deact. this state is triggered by a deactivation request dr, and is an unstable state. indication diu (state g4 unackn.) is issued by the sbc when: C either info0 is received during 16 ms C or an internal timer of 32 ms expires. g4 unacknowledged final state after a deactivation request. the sbc remains in this state until an acknowledgment to diu (did) is issued, without which a new activation is impossible. test mode continuous pulses continuous alternating pulses are sent. test mode single pulses single alternating pulses are sent (2-khz repetition rate).
semiconductor group 52 operational description figure 26 state diagram of nt mode
semiconductor group 53 operational description example of activation / deactivation an example of an activation/deactivation of the s interface, with the aforementioned time relationships, is shown in figure 27 , in the case of an sbc in te and lt-s modes. figure 27 example of activation / deactivation
semiconductor group 54 4 electrical characteristics absolute maximum ratings stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may effect device reliability. line overload protection the maximum input current (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse ( figure 28 ). figure 28 test condition for maximum input current parameter symbol limit values unit ambient temperature under bias peb 2080 pef 2080 t a t a 0 to 70 C 40 to 85 ?c ?c storage temperature t stg C 65 to 125 ?c voltage on any pin with respect to ground v s C 0.4 to v dd + 0.4 v v power dissipation p d 1w electrical characteristics
semiconductor group 55 electrical characteristics transmitter input current the destruction limits for negative input signals with r i 3 2 w and for positive input signals with r i 3 200 w are given in figure 29 . figure 29 receiver input current the destruction limits are given in figure 30 . r i 3 300 w . figure 30
semiconductor group 56 electrical characteristics notes: 1) due to the transformer, the load resistance as seen by the circuit is four times r l . 2) the required 20 w output impedance is realised by external components. 3) the 80 w output impedance is required as external resistor. dc characteristics t a = 0 to 70 ?c; v dd = 5 v 5 %, v ss = 0 v parameter symbol limit values unit test condition min. max. l-input voltage v il C 0.4 0.8 v h-input voltage v ih 2.0 v dd + 0.4 v l-output voltage l-output voltage (sdo) v ol v ol1 0.45 0.45 v v i ol = 2 ma i ol = 7 ma h-output voltage h-output voltage v oh v oh 2.4 v dd C 0.5 v v i oh = C 400 m a i oh = C 100 m a power supply current operational i cc 13 ma peb 2080; v dd = 5 v inputs at v ss / v dd no output loads power down 1 ma power supply current operational i cc 15 ma pef 2080; v dd = 5 v inputs at v ss / v dd no output loads power down 1.3 ma input leakage current output leakage current i li i lo 10 m a 0v < v in < v dd to 0 v 0v < v in < v dd to 0 v absolute value of output pulse amplitude (vsx2 - vsx1) v x 2.03 2.10 2.31 2.39 v v r l = 50 w 1) 2) r l = 400 w 1) 2) transmitter output current i x 7.5 13.4 ma r l = 5.6 w 1) transmitter output impedance r x 10 k w inactive or during binary one 80 w during binary zero 3) r l = 50 w receiver output voltage v sr1 2.35 2.6 v i o < 5 m a receiver threshold voltage vsr1 - vsr2 v tr 225 375 mv dependent on peak level
semiconductor group 57 electrical characteristics recommended oscillator circuit figure 31 the integrated oscillator uses a parallel resonance crystal. capacitances t a = C 40 to 85 ?c, v dd = 5 v 5%, v ss = 0 v, f c = 1 mhz parameter symbol limit values unit test condition min. max. input capacitance i/o capacitance c in c io 7 7 pf pf all pins except sr1,2 xtal1,2 output capacitance against v ssa c out 10 pf sx1,2 load capacitance c ld 50 pf xtal1,2 unmeasured pins returned to ground.
semiconductor group 58 electrical characteristics table 6 output stages application te te te lt-t lt-t nt lt-s lt-s lt-s operation of iom interface inverted mode inverted mode iom-1 mode iom-2 mode or invert. mode iom-1 mode iom-1 mode iom-2 mode or invert. mode iom-1 mode iom-1 mode m2 m1 m0 0 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 0 dcl push/ pull push/ pull push/ pull fsc push/ pull push/ pull push/ pull cp push/ pull push/ pull push/ pull push/ pull push/ pull x2 push/ pull push/ pull push/ pull push/ pull x1 push/ pull push/ pull push/ pull push/ pull push/ pull x0 push/ pull push/ pull open drain* sdo push/ pull push/ pull push/ pull open drain push/ pull open drain* open drain push/ pull *) with internal pull-up
semiconductor group 59 electrical characteristics table 7 sbc clock signals input and output pin configurations in te, lt-t and lt-s iom-1 modes an integrated pull-up resistor is connected to sdi. for output pin configurations, see table 6 . *application te te te lt-t lt-t nt lt-s lt-s lt-s operation of iom interface inverted mode inverted mode iom-1 mode iom-2 mode or invert. mode iom-1 mode iom-1 mode iom-2 mode or invert. mode iom-1 mode iom-1 mode m2 m1 m0 0 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 0 dcl o: 512 khz* 1:2 o: 512 khz* 1:2 o: 512 kh z* 2:1 i: 4096 khz i: 512 khz i: 512 khz i: 4096 khz i: 512 khz i: 512 khz fsc o:8 khz* o:8 khz* o:8 khz* i:8 khz o:8 khz* 1:1 i:8 khz i:8 khz i:8 khz cp o: 1536 khz 3:2 o: 1536 khz 3:1 o: 1536 khz 3:2* o: 512 khz* 2:1 o: 512 khz* 2:1 x2 o: 2560 khz 1:2 o: 1280 khz 1:2 o: 192 khz* 1:1 x1 o: 3840 khz 1:1 o: 3840 khz 1:1 o: 3840 khz 1:1 o: 7680 khz 1:1 o: 7680 khz 1:1 x0 i:fixed at 0 i:fixed at 0 *) synchronized to s line
semiconductor group 60 electrical characteristics ac characteristics t a = 0 to 70 ?c, v dd = 5 v 5 % for peb 2080 t a = C 40 to 85 ?c, v dd = 5 v 5 % for pef 2080 the ac testing input/output waveform is shown below. figure 32 input / output waveform for ac test jitter in te mode, the timing extraction jitter of the sbc conforms to ccitt recommendation i.430 (C 7 % to + 7 % of the s-interface bit period). in the nt and lt-s applications, the clock input dcl is used as reference clock to provide the 192-khz clock for the s line interface. in the case of a plesiochronous 7.68-mhz clock generated by an oscillator, the clock dcl should have a jitter of less than 100 ns peak-to-peak. (in the case of a zero input jitter on dcl, sbc generates at most 130 ns self-jitter on s interface.) in the case of a synchronous (fixed divider ratio of 15 between xtal1 and dcl) 7.68-mhz clock (input xtal1), the sbc transfers the input jitter of xtal1, dcl and fsc to the s interface. the maximum jitter of the nt/lt-s output is limited to 260 ns peak-to-peak (ccitt i.430). clock timing the clocks in the different operating modes are summarized in table 7 , with duty ratios. clock cp is phase-locked to the receive s signal, and is derived using the internal dpll and the 7.68 mhz 100 ppm crystal (te and lt-t). a phase tracking of cp with respect to s is performed once in 250 m s. as a consequence of this dpll tracking, the high state of cp may be either reduced or extended by one 7.68 mhz period (cp duty ratio 2:2 or 4:2 instead of 3:2) once every 250 m s. since dcl and fsc are derived from cp (te mode), the high state (fsc) or the high or low state (dcl) may likewise be reduced or extended by the same amount once every 250 m s. (the phase adjustment may take place either in the sixth, seventh or eighth cp cycle counting from the beginning of an iom frame in te). the phase relationships of the auxiliary clocks are shown in figure 29 .
semiconductor group 61 electrical characteristics figure 33 phase relationships of auxiliary clocks tables 8 to 12 give the timing characteristics of the clock. figure 34 definition of clock period and width
semiconductor group 62 electrical characteristics table 8 xtal1,2 table 9 dcl table 10 cp parameter symbol limit values unit min. max. high phase of crystal/clock t w h 20 ns low phase of crystal/clock t w l 20 ns parameter symbol limit values unit test condition min. typ. max. (te) 512 khz t pq 1822 1953 2084 ns osc 100 ppm (te) 512 khz 2:1 t w hq 1121 1302 1483 ns osc 100 ppm (te) 512 khz 2:1 t w lq 470 651 832 ns osc 100 ppm (te) 512 khz 1:2 t w hq 470 651 832 ns osc 100 ppm (te) 512 khz 1:2 t w lq 1121 1302 1483 ns osc 100 ppm (nt, lt-s, lt-t) t w hi 90 ns osc 100 ppm (nt, lt-s, lt-t) t w li 90 ns osc 100 ppm parameter symbol limit values unit test condition min. typ. max. (te) 1536 khz t pq 520 651 782 ns osc 100 ppm (te) 1536 khz t w hq 240 391 541 ns osc 100 ppm (te) 1536 khz t w lq 240 260 281 ns osc 100 ppm (te, lt-t) t r , t f 20 10 ns c l = 100 pf c l = 50 pf (lt-t) 512 khz t pq 1822 1953 2084 ns osc 100 ppm (lt-t) 512 khz t w hq 1121 1302 1483 ns osc 100 ppm (lt-t) 512 khz t w lq 470 651 832 ns osc 100 ppm
semiconductor group 63 electrical characteristics table 11 x1 table 12 x2 parameter symbol limit values unit test condition min. typ. max. (te) 3840 khz t pq C 100 ppm 260 100 ppm ns osc 100 ppm (te) 3840 khz t w hq 120 130 140 ns osc 100 ppm (te) 3840 khz t w lq 120 130 140 ns osc 100 ppm parameter symbol limit values unit test condition min. typ. max. (te) 2560 khz t pq C 100 ppm 391 100 ppm ns osc 100 ppm (te) 2560 khz t w hq 110 130 150 ns osc 100 ppm (te) 2560 khz t w lq 250 260 270 ns osc 100 ppm (te) 1280 khz t pq C 100 ppm 781 100 ppm ns osc 100 ppm (te) 1280 khz t w hq 250 260 270 ns osc 100 ppm (te) 1280 khz t w lq 511 521 531 ns osc 100 ppm
semiconductor group 64 electrical characteristics cp, dcl and fsc relationships in iom ? master mode figure 35 parameter symbol limit values unit test condition min. max. clock delay cp - dcl t d c 050ns c l = 100 pf clock delay cp - fsc t f c 050ns c l = 100 pf delay dcl - fsc t f d C 20 20 ns c l = 100 pf
semiconductor group 65 electrical characteristics iom ? interface normal mode master mode (te) figure 36 parameter symbol limit values unit min. max. frame sync delay c l = 100 pf t f d C 20 20 ns iom output data delay c l = 100 pf t i od 200 ns iom input data setup t i is 20 ns iom input data hold t i ih 50 ns
semiconductor group 66 electrical characteristics slave mode (nt, lt-s, lt-t) figure 37 parameter symbol limit values unit min. max. frame sync hold t f h 30 ns frame sync setup t f s 50 ns frame sync high t f wh 40 ns frame sync low t f wl 2150 ns iom data output delay t i od 200 ns* ) iom input data setup t i is 20 ns iom input data hold t i ih 50 ns *) for push-pull output. for open drain output with integrated pull-up resistor, the maximum value is 900 ns.
semiconductor group 67 electrical characteristics inverted mode figure 38 parameter symbol limit values unit min. max. frame sync delay c l = 100 pf t f sd C 20 20 ns iom output data delay c l = 100 pf t i od 200 ns iom input data setup t i is 20 ns iom input data hold t i ih 50 ns
semiconductor group 68 electrical characteristics inverted mux mode figure 39 parameter symbol limit values unit min. max. frame sync hold t f h 50 ns frame sync setup t f s 20 ns frame sync high t f wh 124.8 m s frame sync low t f wl 70 200 ns iom data output delay c l = 150 pf; i ol = 7 ma t i od 200 ns iom input data setup t i is 20 ns iom output data hold t i ih 50 ns
semiconductor group 69 electrical characteristics timing of special function pins rst characteristics rdy characteristics figure 40 parameter symbol limit values unit min. max. length of active (low) state t w l 1ms parameter symbol limit values unit min. max. length of low state t w l 360 m s length of high state t w h 60 m s
semiconductor group 70 electrical characteristics de characteristics the form of the de input/output (pin x0, nt mode) is given by figure 41 for the case of two s interfaces having a minimum frame delay and a maximum frame delay, respectively. figure 41 star configuration in nt the ac characteristics of de output and input are shown in figure 42 and 43 and table 13 .
semiconductor group 71 electrical characteristics figure 42 timing of de output figure 43 timing of de input table 13 parameter symbol limit values unit min. max. de delay c l = 100 pf t ded 2 m s de setup t des 3 m s de hold t deh 0 m s
semiconductor group 72 electrical characteristics figure 44 timing of de
semiconductor group 73 electrical characteristics echo characteristics the timing of the echo output (pin x2, te mode) is identical with that of output sdo: however, the signal is 1 everywhere except in bit positions 24 and 25 (d-bit positions) of iom frame, where it is equal to the e bits received from the s interface. adaptive receiver characteristics the integrated receiver uses an adaptively switched threshold detector. the detector controls the switching of the receiver between two sensitivity levels. the hysteresis characteristics of the receiver are shown in figure 45 . figure 45 switching of the receiver between high sensitivity and low sensitivity
semiconductor group 75 5 package outlines plastic dual-in-line package, p-dip-22 plastic-leaded chip carrier, p-lcc-28-r (smd) smd = surface mounted device dimensions in mm package outlines

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